Random access memory (“RAM”) is the place in a computer where the operating system, application programs, and data in current use are kept so that they can be quickly reached by the computer's processor. RAM is much faster to read from and write to than the other kinds of storage in a computer such as the hard disk, a floppy disk, or a compact disk read only memory (“CD-ROM”). However, the data in RAM stays there only as long as the computer is running. When the computer is turned off, RAM loses its data. When the computer is turned on again, the operating system and other files are once again loaded into RAM, usually from the hard disk.
Typically, RAM is packaged in discrete microchip devices that plug into sockets in the computer's motherboard or memory boards. These sockets connect through a bus or set of electrical paths to the processor. The amount of RAM used in current computers systems may be in the gigabytes and is constantly increasing. Having more RAM in a computer reduces the number of times that the computer processor has to read data in from the hard disk, an operation that takes much longer than reading data from RAM. (RAM access time is expressed in nanoseconds; hard disk access time is expressed in milliseconds.)
RAM is called “random access” because any storage location can be accessed directly. Internally, RAM is organized and controlled in a way that enables data to be stored and retrieved directly to specific locations. In general, RAM is much like an arrangement of post-office boxes in which each box can hold a 0 or a 1. Each box has a unique address that can be found by counting across columns and then counting down by row. In RAM, this set of post-office boxes is known as an array and each box is a “cell”. To find the contents of a box (cell), the RAM controller sends the column/row address down a very thin electrical line etched into the chip. There is an address line for each row and each column in the set of boxes. If data is being read, the bits that are read flow back on a separate data line. In describing a RAM chip or module, a notation such as 256K×16 means 256 thousand columns of cells standing 16 rows deep. In the most common form of RAM, dynamic RAM (“DRAM”), each cell has a charge or lack of charge held in something similar to an electrical capacitor. A transistor acts as a gate in determining whether the value in the capacitor can be read or written. In static RAM (“SRAM”), instead of a capacitor-held charge, the transistor itself is a positional flip/flop switch, with one position meaning 1 and the other position meaning 0.
When the processor or CPU gets the next instruction it is to perform, the instruction may contain the address of some memory or RAM location from which data is to be read (i.e., brought to the processor for further processing). This address is sent to the RAM controller. The RAM controller organizes the request and sends it down the appropriate address lines so that transistors along the lines open up the cells so that each capacitor value can be read. A capacitor with a charge over a certain voltage level represents the binary value of 1 and a capacitor with less than that charge represents a 0. For DRAM, before a capacitor is read, it must be power-refreshed to ensure that the value read is valid. Generally, the entire line of data is read that the specific address happens to be located at. The data that is read is transmitted along the data lines to the processor's nearby data buffer known as a level-1 cache and another copy may be held in a level-2 cache.
The amount of time that RAM takes to write data or to read it once the request has been received from the processor is called the access time. Typical access times vary from 9 nanoseconds to 70 nanoseconds, depending on the kind of RAM. Although fewer nanoseconds is better, user-perceived performance is based on coordinating access times with the computer's clock cycles. Access time consists of latency and transfer time. Latency is the time to coordinate signal timing and refresh data after reading it.
The main RAM in a computer typically consists of SRAM and DRAM. As mentioned above, DRAM uses a kind of capacitor that needs frequent power refreshing to retain its charge. Because reading a DRAM discharges its contents, a power refresh is required after each read. Apart from reading, just to maintain the charge that holds its content in place, DRAM must be refreshed about every 15 microseconds. DRAM is the least expensive kind of RAM. SRAM is RAM that retains data bits in its memory as long as power is being supplied. Unlike DRAM, which stores bits in cells consisting of a capacitor and a transistor, SRAM does not have to be periodically refreshed. SRAM provides faster access to data and is more generally more expensive than DRAM. SRAM is typically used for a computer's level-1 and level-2 caches which the microprocessor looks in first before looking in DRAM.
Cache memory is RAM that a computer's microprocessor can access more quickly than it can access regular RAM. As the microprocessor processes data, it looks first in the cache memory and if it finds the data there (i.e., from a previous reading of data), it does not have to do the more time-consuming reading of data from larger memory. Cache memory is sometimes described in levels of closeness and accessibility to the microprocessor. Thus, a level-1 cache is on the same chip as the microprocessor while a level-2 cache is usually a separate SRAM chip. The main RAM is usually a DRAM chip.
There are, of course, may other types of RAM. For example, burst static RAM (“BSRAM”) is synchronized with the system clock or, in some cases, the cache bus clock. This allows it be more easily synchronized with any device that accesses it and reduces access waiting time. It is often used as external level-2 cache memory in microprocessor chipsets. Enhanced DRAM (“EDRAM”) is the combination of SRAM and DRAM in a single package that is usually used for a level-2 cache. Typically, 256 bytes of SRAM is included along with the DRAM. Data is read first from the faster (typically 15 nanoseconds) SRAM and if it is not found there, it is read from the DRAM, typically at 35 nanoseconds. Non-volatile RAM (“NVRAM”) is a special kind of RAM that retains data when the computer is turned off or there is a power failure. Like the computer's read-only memory (“ROM”), it is powered by a battery within the computer. It can also work by writing its contents to and restoring them from an electrically erasable programmable read-only memory (“EEPROM”). Synchronous DRAM (“SDRAM”) is a generic name for various kinds of DRAM that are synchronized with the clock speed that the microprocessor is optimized for. This tends to increase the number of instructions that the processor can perform in a given time. The speed of SDRAM is rated in MHz rather than in nanoseconds (ns). This makes it easier to compare the bus speed and the RAM chip speed. Double data rate SDRAM (“DDR SDRAM”) can theoretically improve RAM speed to at least 200 MHz. It activates output on both the rising and falling edge of the system clock rather than on just the rising edge, potentially doubling output. And, enhanced SDRAM (“ESDRAM”) includes a small SRAM in the SDRAM chip. This means that many accesses will be from the faster SRAM. In case the SRAM doesn't have the data, there is a wide bus between the SRAM and the SDRAM because they are on the same chip. Note that EDRAM and ESDRAM also known as “cached DRAM”.
Thus, RAM is one of the key components of any computer system. Accordingly, its proper functioning is critical to computer performance. As such, RAM must be properly and effectively tested. However, RAM devices are becoming increasingly complicated which makes their testing both more difficult and more important. This is especially so for RAM devices that include an internal cache (such as EDRAM and ESDRAM).
One problem with current methods of testing RAM is that internal caching within the RAM device may not be properly accounted for. As such, these current methods may yield false results. In particular, such tests may only access the internal cache section of the RAM device rather than the main memory section.
A need therefore exists for an improved method and system for testing a RAM device having an internal cache. Accordingly, a solution that addresses, at least in part, the above and other shortcomings is desired.